View ICS872S480_4670442.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet ICS872S480bk revision a april 19, 2011 1 ?2011 integrated device technology, inc. differential-to-hstl zero delay clock generator ICS872S480 9 10111213141516 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 clk0 nclk0 gnd clk1 nclk1 pll_bypass fb_in nfb_in v dd lor0 lor1 clk_ind gnd freq_sel oe v dda nqfb qfb v dd nq1 q1 nq0 q0 v dd v dd ref_sel auto_sel nc gnd vout_sel v dd nc general description the ICS872S480 is a zero delay clo ck generator with hitless input clock switching capability. the ICS872S480 is ideal for use in redundant, fault tolerant clock trees where low jitter frequency synthesis are critical. the device receives two differential clock signals from which it generates two outputs with ?zero? delay. the output and feedback dividers are configured to allow for a 1:1 frequency generation ratio. the ICS872S480 dynamic clock swit ch (dcs) circuit continuously monitors both input clock signals. upon detection of an invalid clock input (stuck low or high for at least one complete clock period of the vco feedback frequency), the loss of reference monitor will be set high. if that clock is the primary clock, the dcs will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturb ance. once the primary clock is restored to a good state, the dcs will automatically switch back to the primary clock input. the low jitter characteristics with input clock monitoring and dcs capability make the ICS872S480 an ideal choice for ddr3 applications requiring fault tolerant reference clocks. features ? three differential hstl output pairs ? selectable differential clkx, nclkx input pairs ? clkx, nclkx pairs can accept the following differential input levels: lvpecl, lvds, hstl, hcsl ? output frequency range: 350mhz to 950mhz ? input frequency range: 350mhz to 950mhz ? vco range: 970mhz to 2250mhz ? external feedback for ?zero delay? clock regeneration with configurable frequencies ? static phase offset: 100ps (maximum) ? cycle-to-cycle jitter: 25ps (maximum) ? output skew: 20ps (maximum) ? 3.3v operating voltage supply ? selectable ddr3 or ddr3 low voltage output ? 0c to 70c ambient o perating temperature ? available in lead-free (rohs 6) package ICS872S480 32-lead vfqfn 5mm x 5mm x 0.925mm package body k package top view pin assignment function table input output divider input & output frequency (mhz) freq_sel minimum maximum 0 2 485 950 1 (default) 4 350 562.5 output voltage table input hstl output style vout_sel 0 (default) 1.5v 1 1.35v
ICS872S480bk revision a april 19, 2011 2 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator block diagram pd + cp + lf pll_bypass output divider activity detector activity detector 0 1 dynamic switch logic 1 0 lor0 lor1 ref_sel auto_sel vco 1 0 oe qfb, nqfb q0, nq0 q1, nq1 freq_sel clk_ind vout_sel pulldown pulldown pulldown pullup pullup pullup clk0 nclk0 pullup pulldown pullup pulldown pullup pulldown clk1 nclk1 fb_in nfb_in
ICS872S480bk revision a april 19, 2011 3 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1 clk0 input pulldown non-inverting differential clock input. 2 nclk0 input pullup inverting differential clock input. 3, 20, 28 gnd power power supply ground. 4 clk1 input pulldown non-inverting differential clock input. 5 nclk1 input pullup inverting differential clock input. 6 pll_bypass input pulldown pll bypass pin. when high, the pll is bypassed and the reference clock is passed directly to the output dividers. lvcmos/lvttl interface levels. 7 fb_in input pulldown non-inverting differential external feedback input. 8 nfb_in input pullup inverting differential external feedback input. 9, 10 nqfb, qfb output differentia l feedback output pair. hstl interface levels. see table 4d. 11, 16, 24, 25, 32 v dd power core supply pins. 12, 13 nq1, q1 output differential outp ut pair. hstl interface levels. 14, 15 nq0, q0 output differential outp ut pair. hstl interface levels. 17 v dda power analog supply pin. 18 oe input pullup output enable pin. lvcmos/lvttl interface levels. 19 freq_sel input pullup frequency select pin. lvcmos/lvttl interface levels. 21 clk_ind output clock indicator pin. when low, clk0, nclk0 is selected. when high, clk1, nclk1 is selected. 22 lor1 output loss of reference indicator for cl k1, nclk1. lvcmos/lvttl interface levels. 23 lor0 output loss of reference indicator for cl k0, nclk0. lvcmos/lvttl interface levels. 26 vout_sel input pulldown output voltage select pi n. lvcmos/lvttl interface levels. 27, 29 nc unused no connect. 30 auto_sel input pullup dynamic clock switch enable pin. when low, disables internal dynamic clock switch circuitry and clk_indicator will track ref_sel. when high, dynamic clock switch is enabled. lvcm os/lvttl interface levels. 31 ref_sel input pulldown reference clock select pin. when low selects clk0, nc lk0, when high selects clk1, nclk1. lvcmos/lvttl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 2pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ICS872S480bk revision a april 19, 2011 4 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 42.7 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ?0.25 3.3 v dd v i dd power supply current outputs terminated 50 ? to gnd 275 ma i dda analog supply current 25 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current pll_bypass, ref_sel, vout_sel v dd = v in = 3.465v 150 a oe, freq_sel, auto_sel v dd = v in = 3.465v 10 a i il input low current pll_bypass, ref_sel, vout_sel v dd = 3.465v, v in = 0v -10 a oe, freq_sel, auto_sel v dd = 3.465v, v in = 0v -150 a
ICS872S480bk revision a april 19, 2011 5 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator table 4c. differential dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . table 4d. hstl dc characteristics, v dd = 3.3v 5%, t a = 0c to 70c note 1: outputs terminated with 50 ? to ground. table 5. input frequency characteristics, v dd = 3.3v 5%, t a = 0c to 70c symbol parameter test conditio ns minimum typical maximum units i ih input high current clk0, clk1, fb_in v dd = v in = 3.465v 150 a nclk0, nclk1, nfb_in v dd = v in = 3.465v 10 a i il input low current clk0, clk1, fb_in v dd = 3.465v, v in = 0v -10 a nclk0, nclk1, nfb_in v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.75 v v cmr common mode input volt age; note 1, 2 0.3 v dd ? 0.85 v symbol parameter test conditions minimum typical maximum units v ox output crosspoint voltage, note 1 vout_sel = 0 0.7 0.8 0.9 v vout_sel = 1 0.6 0.7 0.8 v v od differential output voltage; note 1 vout_sel = 0 0.8 0.9 1.0 v vout_sel = 1 0.8 0.9 1.0 v symbol parameter test conditio ns minimum typical maximum units f in input frequency clk0, nclk0, clk1, nclk1 fsel = 1 485 950 mhz fsel = 0 350 562.5 mhz
ICS872S480bk revision a april 19, 2011 6 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator ac electrical characteristics table 6. ac characteristics, v dd = 3.3v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: defined as the time difference between the input refer ence clock and the averaged feedback input signal across all cond itions, when the pll is locked and the input reference frequency is stable. c haracterized using hstl input le vel of 900mv, swing centered ar ound 0.6v. note 2: this parameter is defined in accordance with jedec standard 65. note 3: this parameter is defined as the maximum output period deviation during a dynamic switch event with reference inputs 18 0 out of phase. this does not factor in any cycle-to -cycle jitter seen on the input or output. note 4: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the output diffe rential cross points. note 5: output slew rate is measured at v ox 150mv for vout_sel = 0 and v ox 135mv for vout_sel = 1. note 6: this parameter is defined as pll lock time after a dynamic switch event with reference inputs 180 out of phase. note 7: this parameter is guaranteed by characterization. not tested in production. symbol parameter test conditions minimum typical maximum units f out output frequency 350 950 mhz t (?) static phase offset; note 1, 2 f out = 400mhz -25 75 ps f out = 533.3mhz -50 50 ps f out = 666.6mhz -50 50 ps f out = 800mhz -50 50 ps tdyn (?) dynamic phase offset; note 7 f out = 400mhz 20 ps f out = 533.3mhz 25 ps f out = 666.6mhz 20 ps f out = 800mhz 20 ps pdev output period deviation; note 3, 7 100 ps t sk(o) output skew; note 2, 4 20 ps t jit(cc) cycle-to-cycle jitter; note 3, 7 25 ps t l pll lock time; note 7 3ms t ldcs dcs pll lock time; note 6, 7 1.7 s t slew output slew rate; note 5 vout_sel = 0 f out = 400mhz 2.00 3.50 5.75 v/ns f out = 533.3mhz 2.00 4.25 6.50 v/ns f out = 666.6mhz 2.00 4.25 6.75 v/ns f out = 800mhz 2.50 5.25 8.65 v/ns vout_sel = 1 f out = 400mhz 2.00 3.85 6.35 v/ns f out = 533.3mhz 2.00 4.50 6.85 v/ns f out = 666.6mhz 2.50 4.65 7.25 v/ns f out = 800mhz 3.00 5.65 8.25 v/ns odc output duty cycle 47 53 %
ICS872S480bk revision a april 19, 2011 7 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator parameter measureme nt information 3.3v output load ac test circuit cycle-to-cycle jitter static phase offset differential input level output skew output duty cycle/pulse width/period scope hstl qx nqx gnd 0v v dda 3.3v 5% 3.3v 5% v dd nq[0:1] q[0:1] ? ? ? ? cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles nclk[0:1] clk[0:1] nfb_in fb_in ? ? (?) t (?) mean = static phase offset (where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on controlled edges) nclk0, nclk1 clk0, clk1 v dd gnd v cmr cross points v pp nqx qx nqy qy t sk(o) t pw t period t pw t period odc = x 100% nq[0:1] q[0:1]
ICS872S480bk revision a april 19, 2011 8 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator parameter measurement in formation, continued dynamic phase offset slew rate pll lock time ? ? t (?) histogram dynamic phase offset dynamic phase offset = ? t (?) ? t (?) mean ? t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on the controlled edges ? t (?) mean nclk[0:1] nclk[0:1] nfb_in fb_in ? ? ?
ICS872S480bk revision a april 19, 2011 9 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator applications information clock redundancy and reference selection the ICS872S480 accepts two differential input clocks, clk0, nclk0 and clk1, nclk1, for the purpose of redundancy. only one of these clocks can be selected at any given time for use as the reference. clk0, nclk0 is defined as the initial, or primary clock, while the remaining clock is the redundant or secondary clock. the output signal clk_ind indicates which clock input is being used as the reference (low = clk0, nclk0, high = clk1, nclk1). failure detection and alarm signaling within the ICS872S480 device, clk0, nclk0 and clk1, nclk1 are continuously monitored for failures. a failure on either of these clocks is detected when one of the clock signals is stuck high or low for at least 1 period of the feedback. upon detection of a failure, the corresponding loss-of-reference signal, lor0 or lor1, will be set high. the input clocks are continuously monitored and the loss-of-reference signals will continue to reflect the real-time status of each input clock. manual clock switching when input signal auto_sel is driven low, the clock specified by ref_sel will always be used as the reference, even when a clock failure is detected at the reference. in order to switch between clk0, nclk0 and clk1, nclk1 as the reference clock, the level on ref_sel must be driven to the appropriate level. when the level on ref_sel is changed, the selection of the new clock will take place, and clk_ind will be updated to indicate which clock is now supplying the reference to the pll. dynamic clock switching the dynamic clock switching (dcs) process serves as an automatic safety mechanism to protect the st ability of the pll when a failure occurs on the reference. when input signal auto_sel is not driven high, an internal pullup pulls it high so that dcs is enab led. if dcs is enabled and a failure occurs on the initial clock, the ICS872S480 device will check the status of the secondary clock. if the secondary clock is detected as a good input clock, the ICS872S480 will automatically de-select the initial clock as the reference and multiplex in the secondary clock. when a successful switch from t he initial to secondary clock has been accomplished, clk_ind will be updated to indicate the new reference. if and when the fault on the initial clock is corrected, the corresponding loss-of-reference flag will be updated to represent this clock as good again. once updated, the dcs will undergo an automatic clock switch. see th e dynamic clock switch state diagram and for additional details on the functionality of the dynamic clock switching circuit. output transitioning after a successful dcs initiated clock switch, the internal pll of the ICS872S480 will begin slewing to phase/frequency alignment of the newly selected clock input. the pll will achieve lock to the new input with minimal phase distur bance at the outputs. recommended power-up sequence 1.before startup, set auto_sel low so the pll will operate in manual switch mode, plus set ref_sel low to ensure that the primary reference clock, clk0, nclk0, is selected. this will ensure that during startup, the pll will acquire lock using the primary reference clock input. 2.once powered-up, and assuming a stable clock is present at the primary clock input, the pll will begin to phase/frequency slew as it attempts to achieve lock with the input reference clock. 3.drive auto_sel high to enable dcs mode. alternate power-up sequence if both input clocks are valid before power up, the part may be powered-up in dcs mode. however, it cannot be guaranteed that the pll will achieve lock with one specific input clock. 1.before startup, leave auto_sel floating and the internal pullup will enable dcs mode. 2.once powered up, the pll will begin to phase/frequency slew as it attempts to achieve lock with one of the input reference clocks.
ICS872S480bk revision a april 19, 2011 10 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator state diagram
ICS872S480bk revision a april 19, 2011 11 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels
ICS872S480bk revision a april 19, 2011 12 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator differential clock input interface the clk /nclk accepts lvds, lvpecl, hstl, hcsl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figures 3a to 3e show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver co mponent to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt open emitter hstl drivers. if you are using an hstl driver from another vendor, use their termination recommendation. figure 3a. clk/nclk input driven by an idt open emitter hstl driver figure 3c. clk/nclk input driven by a 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 *r4 33 clk nclk 3.3v 3.3v zo = 50 zo = 50 differential input r1 50 r2 50 *optional ? r3 and r4 can be 0 clk nclk differential input lvpecl 3.3v zo = 50 zo = 50 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 zo = 50
ICS872S480bk revision a april 19, 2011 13 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator recommendations for unused input pins inputs: lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. clk/nclk inputs for applications not requiring the us e of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. outputs: hstl outputs all unused hstl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. hstl output termination figure 4. output termination vddo zo = 50 hstl + - ics hiperclocks vdd r2 50 r1 50 zo = 50 hstl hstl driv er
ICS872S480bk revision a april 19, 2011 14 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 5. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 5. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ICS872S480bk revision a april 19, 2011 15 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator schematic example figure 6 shows an example of ICS872S480 application schematic. in this example, the device is operated at v dd = 3.3v. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the ics 872s480 provides separate power supplies to isolate from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the filter componen ts be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pin filter should be placed on the device side of the pcb and the other components can be placed on the opposite side. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of noise frequencies. this low-pass filter st arts to attenuate noise at approximately 10khz. if a specific frequency noise compone nt is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk c apacitance in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. figure 6. ICS872S480 schematic layout vdd1 r5 2.2k ld1 vdd r12 10 r11 50 c2 10u vdd nclk0 (u1, 11) vdd r3 125 pll_by pass r7 84 zo = 50 ohm vdd clk0 zo = 50 ohm vdd r17 50 q0 vdd q1 r1 2.2k to logic input pins lor1 + - nclk1 zo = 50 q0 oe nq0 vdda c1 0.1u ld3 (u1, 25) rd2 1k c4 10uf ru1 1k ru2 not install nq0 r13 84 fb_in r2 125 c3 0.1uf r4 2.2k (u1, 16) 3.3v r8 125 c11 0.1u nfb_in to logic input pins set logic input to '0' zo = 50 set logic input to '1' c6 0.1uf blm18bb221sn1 ferrite bead 1 2 c9 0.1u clk1 r10 50 blm18bb221sn1 ferrite bead 1 2 r14 84 vdd u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 clk0 nclk0 gnd clk1 nclk1 pll_by pass fb_in nfb_in nqfb qfb vdd nq1 q1 nq0 q0 vdd vdda oe freq_sel gnd clk_ind lor1 lor0 vdd vdd ref_sel auto_sel nc gnd nc vout_sel vdd lor0 c7 10uf vout_sel ld2 logic control input examples rd1 not install clk_ind r16 50 lvpecl driv er nq1 c8 0.1u (u1, 32) zo = 50 zo = 50 ohm r6 84 c12 0.1u c5 0.1uf r9 125 r18 50 (u1, 24) 3.3v vdd=3.3v nq1 r15 50 3.3v ref_sel freq_sel q1 + - zo = 50 ohm 3.3v auto_sel vdd c10 0.1u zo = 50 lvpecl driv er
ICS872S480bk revision a april 19, 2011 16 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator power considerations this section provides information on power dissipa tion and junction temperature for the ICS872S480. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for theICS872S480 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. power (core) max = v dd_max * (i dd_max + i dda_max )= 3.465v * (275ma + 25ma) = 1039.5mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bon d pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 42.7c/w per table 7 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 1.040w * 42.7c/w = 114.4c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ja for 32 lead vfqfn, forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 42.7c/w 37.3c/w 33.5c/w
ICS872S480bk revision a april 19, 2011 17 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator reliability information table 8. ja vs. air flow table for a 32-lead vfqfn transistor count the transistor count for ICS872S480 is: 2110 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 42.7c/w 37.3c/w 33.5c/w
ICS872S480bk revision a april 19, 2011 18 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator package outline and package dimensions package outline - k suffix for 32 lead vfqfn table 9. package dimensions reference document: jede c publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 9. to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil singulation n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there are 2 methods of indicating pin 1 corner at the back of the vfqfn package are: 1. type a: chamfer on the paddle (near pin 1) 2. type c: mouse bite on the paddle (near pin 1) jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50
ICS872S480bk revision a april 19, 2011 19 ?2011 integrated device technology, inc. ICS872S480 data sheet differential-to -hstl zero delay clock generator ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 872s480bklf ics72s480bl ?lead-free? 32 lead vfqfn tray 0 c to 70 c 872s480bklft ics72s480bl ?lead-free? 32 lead vfqfn 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ICS872S480 data sheet differential-to -hstl zero delay clock generator disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

▲Up To Search▲

Price & Availability of ICS872S480

	To Download ICS872S480 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .